Semiconductor memory device and manufacturing method thereof

Details Semiconductor memory device and manufacturing method thereof Semiconductor memory device and manufacturing method thereof

1990-12-04

1993-01-05

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257306, 257401, 257503, H 0L 2968, H 0L 2940, H 0L 2348

Patent

active

051775751

ABSTRACT:
Disclosed is a semiconductor memory device having such a structure that a voltage variation on a bit line does not affect a voltage on another bit line. A gate electrode portion branches and extends laterally from a word line and extends almost in parallel with the bit line. First and second impurity regions of a field effect transistor are formed on regions between adjacent word lines, with the gate electrode portion therebetween. A capacitor electrically connected to the second impurity region is formed to cover the bit lines. Since the capacitor is between adjacent bit lines, no voltage variation on one bit line affects a voltage on the other bit lines.

REFERENCES:
"A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit-Line Structure" by Shin'ichiro Kimura et al. IEDM 88 (1988), pp. 596-599.
"3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS" by T. Ema et al., IEDM 88 (1988), pp. 592-595.

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