Apparatus and methods for controlling sensing time in a memory d

Details Apparatus and methods for controlling sensing time in a memory d Apparatus and methods for controlling sensing time in a memory d

1998-12-18

1999-12-28

Tran, Andrew Q.

Static information storage and retrieval

Addressing

Sync/clocking

36518503, 3651852, 36518909, 365210, 36523008, 365194, 365196, 365168, 365236, G11C 800

Patent

active

060090405

ABSTRACT:
An apparatus for controlling reading of memory cells in a memory device includes a word line voltage generator operative to apply a word line voltage to a selected memory cell of memory device responsive to a sensing period signal. A dummy memory cell is coupled to the word line voltage generator such that the word line voltage is applied to the dummy memory cell, the dummy memory cell having a threshold voltage. A sensing period controller is coupled to the dummy memory cell and operative to produce the sensing period signal responsive to a current generated in the dummy memory cell. According to an embodiment of the present invention, the sensing period controller includes a dummy sense amplifier coupled to the dummy memory cell and operative to produce a dummy cell sense amplifier output signal responsive to a current in the dummy memory cell. A sensing time detector is coupled to the dummy sense amplifier and operative to produce a sensing time signal in response to a transition of the dummy cell sense amplifier output signal. A sensing period signal generator is coupled to the sensing time detector and operative to generate the sensing period signal responsive to the sensing time signal. Apparatus for controlling sensing periods in a multi-level memory device, as well as related operating methods, are also described.

REFERENCES:
patent: 5457650 (1995-10-01), Sugiura et al.
patent: 5761132 (1998-06-01), Kim

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