Test method and circuit for semiconductor memory

Details Test method and circuit for semiconductor memory Test method and circuit for semiconductor memory

1998-03-27

1999-12-28

Hoang, Huan

Static information storage and retrieval

Read/write circuit

Testing

36518529, 36523004, G11C 700

Patent

active

060090278

ABSTRACT:
A checkerboard data pattern is written in a semiconductor memory with a simple arrangement. First, memory cell transistors M00-M77 are erased. A test signal TS is turned to "L," an address ax0 to "1," write signals D0, D2, D4 and D6 to "1." This causes "1" to be written in the memory cell transistors even-numbered in both the rows and columns. Then, the test signal TS is turned to "L," an X address ax0 to "0," write signals D1, D3, D5 and D7 to "1." This causes "1" to be written in the memory cell transistors odd-numbered in both the rows and columns. Thus, the checkerboard can be written with a simple arrangement by activating only the least significant bit ax0 of X addresses ax2-ax0.

REFERENCES:
patent: 4502131 (1985-02-01), Giebel
patent: 4744058 (1988-05-01), Kawashima et al.
patent: 5440518 (1995-08-01), Hazani

Affiliated with

Also associated with

Rating

Test method and circuit for semiconductor memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test method and circuit for semiconductor memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test method and circuit for semiconductor memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2386784