Electrostatic discharge protective circuit for reducing an undes

Details Electrostatic discharge protective circuit for reducing an undes Electrostatic discharge protective circuit for reducing an undes

1998-11-09

1999-12-28

Sherry, Michael J.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 56, 361 915, H02H 322

Patent

active

060089741

ABSTRACT:
An electrostatic discharge (ESD) protective circuit for reducing the electron-tunneling phenomena in NMOS devices. Several complementary metal oxide semiconductor (CMOS) devices act as an ESD protective circuit from being destroyed. The CMOS devices are connected to an internal circuit and a power line provide a bias voltage for the devices. The drains of the CMOS devices are connected to a pad to output a driving current. A NMOS device is connected between the internal circuit and the ESD protective circuit for protecting the NMOS devices in the circuit. As an ESD pulse is input into the ESD protective circuit, the NMOS device is then turned on by the pulse. Thus, positive charges on the gate of the NMOS devices in the ESD circuit is conducted into ground. Therefore, the NMOS device between the internal circuit and the ESD circuit can prevent the gate oxide of the NMOS device in the circuit from damage.

REFERENCES:
patent: 5610790 (1997-03-01), Staab et al.

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