Method of manufacturing DRAM cell

Details Method of manufacturing DRAM cell Method of manufacturing DRAM cell

1990-03-08

1991-11-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 40, 437 41, 437 47, 437 60, 437191, 437919, H01L 2170

Patent

active

050682008

ABSTRACT:
This invention relates to a method of manufacturing a DRAM cell which has a stacked capacitor and forming drain and source polycrystalline silicon regions on surface of a semiconductor substrate. The invention is directed to: a first step for forming a field oxide film and channel stopper as well as a polycrystalline silicon oxide film doped with impurities; a second step for dividing said silicon into a drain and source polycrystalline silicon region and forming a gate oxide film between the two silicon regions simultaneously with the drain and source diffusion regions and a gate electrode on the gate nitride film; a third step for forming an insulating film on the upper surface of the nitride film and a window on the source polycrystalline silicon region, a storage poly contacting with the same through the window; a fourth step for forming a dielectric layer and a plate poly of the stacked capacitor; and a fifth step forming another insulating film thereon and forming a window on the drain polycrystalline silicon region and also forming a bit line contacting with the exposed drain polycrystalline silicon region through that window. This invention can prevent the generation of leakage current resulting from the damage caused by the drain and source diffusion polycrystalline silicon regions when an etching process is used for the formation of the storage poly and the bit line.

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