Membrane dielectric isolation IC fabrication

Details Membrane dielectric isolation IC fabrication Membrane dielectric isolation IC fabrication

1998-02-23

1999-12-28

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438668, H01L 21311

Patent

active

060081260

ABSTRACT:
General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

REFERENCES:
patent: 5367189 (1994-11-01), Nakamura
patent: 5426072 (1995-06-01), Finnila
patent: 5432104 (1995-07-01), Sato
patent: 5445107 (1995-08-01), Roth et al.
patent: 5500554 (1996-03-01), Sato
patent: 5506163 (1996-04-01), Moriya

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