Semiconductor memory device having a plurality of well regions o

Details Semiconductor memory device having a plurality of well regions o Semiconductor memory device having a plurality of well regions o

1993-06-04

1995-04-04

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257204, 257206, 257208, 257296, 257298, 257300, 257372, 257373, H01L 4900, H01L 2968, H01L 2702, H01L 2978

Patent

active

054040426

ABSTRACT:
A semiconductor memory device in accordance with the present invention includes a plurality of n well regions and p well regions in a p type silicon substrate. One of the p well regions is connected to an external power supply. Peripheries of the p well region having a memory cell array formed therein are surrounded by an n well region having a potential held at a positive potential. The n well region held at the positive potential prevents electrons introduced into the substrate due to undershoot from entering into a p well region through the p well region connected to the external power supply.

REFERENCES:
patent: 4163245 (1979-07-01), Kinoshita
patent: 4497045 (1985-12-01), Iizuka et al.
"A New Twin-Well CMOS Process Using Nitridized-Oxide-LOCOS (NOLOCOS) Isolating Technology," IEEE Electric Device Letters, vol. 10, No. 7, Jul. 1989, pp. 307-309.
"A 0.5.mu.m Isolation Technology Using Advanced Poly Silicon Pad LOCOS (APPL)," IEEE IEDM 1988, pp. 100-103.
"An Advanced Half-Micrometer CMOS Device with Self-Aligned Retrograde Twin-Wells and Buried p.sup.+ Layer," VLSI Symposium, 1989, pp. 35-36.

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