Soft error resistant data storage cells

Static information storage and retrieval – Systems using particular element – Flip-flop

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Details

365156, 365181, 365190, G11C 1100

Patent

active

048520608

ABSTRACT:
A CMOS data cell having increased immunity to single event upsets is disclosed. The cell includes a first CMOS inverter and a second CMOS inverter which have their respective storage nodes interconnected by cross-coupling connections. The respective storage nodes of the cell are connected through word line or write clock transfer gates to bit lines or data bus lines which serve to both write in and read out the data state of the cell. The soft error resistant data cell further includes six transistors which provide the hardening features to the data storage cell design. Two data state control transistors (one for each storage node) have their drain electrodes connected to a data storage node and their source electrodes connected to the power supply rail. Each of the data state control transistors is gated by the word line voltage via a transfer device or pass transistor that is in turn, gated by the complementary storage node on the opposite side of the cell. The gate electrode of each of the two data state control transistors is also connected to the drain electrode of a transistor of a cross-coupled transistor pair. Each of two transistors of this cross-coupled transistor pair has its gate electrode cross-coupled to the drain electrode of the other transistor and its source electrode connected to the power supply rail.

REFERENCES:
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patent: 4545036 (1985-10-01), Segers
patent: 4550390 (1985-10-01), Akashi
patent: 4725981 (1988-02-01), Rutledge
patent: 4782467 (1988-11-01), Belt et al.
patent: 4797804 (1989-01-01), Rockett, Jr.

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