Error correction coding and decoding method, and circuit using s

Details Error correction coding and decoding method, and circuit using s Error correction coding and decoding method, and circuit using s

1998-03-26

2000-04-18

Baker, Stephen M.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714785, H03M 1300

Patent

active

060528206

ABSTRACT:
In the coding and decoding of Reed-Solomon codes formed of symbols larger than information symbols, redundant circuitry is eliminated, error detection and correction are performed using a simple construction, and the reliability of error detection and correction is improved by processing only data of the same size as the information symbols. Two bits of dummy data which are surplus bits in 10 bits of one symbol of information are supplied from a dummy data input circuit to 8 bit input data. At the same time, syndrome data is generated from the surplus parts of check symbols by a syndrome data correction circuit. A part of the 10 bit data is selected by a selector, and supplied to a Galois field summation circuit. The output of the Galois field summation circuit is output to a register, and the output of this register is either selected without modification or via a Galois field coefficient multiplying circuit by a selector, and supplied to the Galois field summation circuit. The output of the register is output as syndrome data by a syndrome output terminal.

REFERENCES:
patent: 4782490 (1988-11-01), Tenengolts
patent: 4856003 (1989-08-01), Weng
patent: 4897839 (1990-01-01), Yamagishi et al.
patent: 4972417 (1990-11-01), Sako et al.
Douglas C. Bossen, Lih C. Chang & Chin-Long Chen "Measurement and Generation of Error Correcting Codes for Package Failures" 1978 IEEE pp. 201-204.
C. L. Chen & M. Y. Hsiao "Error-Correcting Codes for Semiconductor Memory Applications: A State-of-the-Art Review" IBM J. Res. Develop., Mar. 1984 pp. 124-134.
Shigeo Kaneda "A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications" IEEE 1984 pp. 737-739.

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