Memory array of inversion controlled switches

Details Memory array of inversion controlled switches Memory array of inversion controlled switches

1978-01-03

1978-10-24

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Semiconductive

307238, 365175, G11C 1140

Patent

active

041225457

ABSTRACT:
The present invention relates to a memory circuit including an array of inversion controlled switches arranged in an arbitrary number of rows and columns. Each inversion controlled switch is provided with emitter, base and collector terminals, and is characterized by first and second impedance states between its emitter and collector terminals. The memory circuit further includes voltage means coupled with the inversion controlled switches of the array for applying a selectively controllable voltage across the emitter and collector terminals of these switches in selected ones of the rows; a plurality of rectifier means each coupled with the base terminal of a respective inversion controlled switch; current means coupled with the rectifier means for applying a current level to the base terminals of the inversion controlled switches in selected ones of the columns through the rectifier means; and data sensing means coupled with the inversion controlled switches in individual ones of the columns for sensing the impedance state of a selected one of the switches in a respective one of the columns.

REFERENCES:
patent: 3796931 (1974-03-01), Maute
patent: 3949243 (1976-04-01), Sander et al.
patent: 3979613 (1976-09-01), Kroger

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