Semiconductor device with reduced fringe capacitance and short c

Details Semiconductor device with reduced fringe capacitance and short c Semiconductor device with reduced fringe capacitance and short c

1997-03-07

2000-04-18

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257276, 257386, 257410, 438216, H01L 2976, H01L 31062

Patent

active

060518618

ABSTRACT:
A semiconductor device and a method of producing the same are disclosed. Cavities intervene between a gate electrode and a source and a drain region for reducing a capacitance. The cavities successfully reduce a fringe capacitance between the gate electrode and the source and drain regions. The side walls are lower in height than the gate electrode, so that the electrode protrudes upward over the top of the side walls. Insulation films are etched back in order to expose the surfaces of the gate electrode and source and drain electrodes. Thereafter, silicide is formed on the gate electrode and a substrate. This allows the gate electrode and source and drain electrodes to be wired via the silicide and thereby reduces the resistance of the device.

REFERENCES:
patent: 3886584 (1975-05-01), Cook, Jr. et al.
patent: 4638347 (1987-01-01), Iyer
patent: 4697333 (1987-10-01), Nakahara
patent: 5389557 (1995-02-01), Jung-Suk
patent: 5587343 (1996-12-01), Kano et al.
J. Huang et al., Electronics Letters, "Vacuum-Insulated-Gate Field-Effects Transistor." vol. 25, No. 23 pp. 1571-1573 (1989).
Hori et al., "Quarter-Micrometer SPI (Self-Aligned Pocket Implantation) MOSFET's And Its Application For Low Supply Voltage Operation", IEEE Transactions ON Electron Devices, Vol. 42(1):78-85, (1995).

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