Method for eliminating transition direction sensitive timing ske

Details Method for eliminating transition direction sensitive timing ske Method for eliminating transition direction sensitive timing ske

1995-12-20

1998-01-06

Butler, Dennis M.

395306, 395558, 395559, G06F 104

Patent

active

057064849

ABSTRACT:
A source synchronous computer system to ensure the capturing of signals transmitted from a first component to a second component. An integrated circuit operating on a core clock signal and an I/O clock signal, the integrated circuit comprising a plurality of data drivers, an external I/O clock generator for transmitting the I/O clock signal, and an inverting external I/O clock generator for transmitting the compliment of the I/O clock signal, wherein the data drivers output data synchronous to the I/O clocks and both transmitted clock signals are combined in a receiving component to form a third clock. The receiving component capturing the outputted data synchronous to the third clock. By outputting data signals in the I/O clock domain and using the combination of the transmitted clock signals to synchronize transmission between external components, the computer system ensures that various output conditions that shift the rising or falling edge of a synchronizing clock are adjusted for by the receiving component generating a third clock that selects the later of the rising or falling clock edge between the transmitted clock signals. A set of data signals, the transmitted I/O clock signal, and the transmitted compliment I/O clock signal are generated from similar drivers and share a common power supply plane to further ensure that the data signals are asserted before the clocking edge of the generated third clock.

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