Method and apparatus for testing hardware interrupt service rout

Details Method and apparatus for testing hardware interrupt service rout Method and apparatus for testing hardware interrupt service rout

1994-06-03

2000-01-25

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 30, G06F 1300

Patent

active

060188081

ABSTRACT:
A read/writable memory formed in the same semiconductor chip as a microprocessor is employed in testing a plurality of hardware interrupt service routines initiated by corresponding devices (and components of devices) during a power-on, self-test(POST) of a computer system. The POST is set in the read-only memory(ROM) of the computer system. The read/writable memory, which is ordinarily inoperative during the POST, is used for storing a diagnostic interrupt vector table, which has a list of interrupt numbers and corresponding addresses of the respective interrupt routines. This table is normally subject to change because each device and each of its components have different interrupt service routines, requiring different addresses for the same interrupt number. The random access memory(RAM) has not yet been tested in the POST, and is not regarded as reliable for the hardware interrupt testing and therefore the read/writable memory is used for such testing.

REFERENCES:
patent: 5182811 (1993-01-01), Sakamara
patent: 5230052 (1993-07-01), Dayan et al.
patent: 5245615 (1993-09-01), Tren
patent: 5291585 (1994-03-01), Sato et al.

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