Programmable dynamic random access memory (DRAM)

Details Programmable dynamic random access memory (DRAM) Programmable dynamic random access memory (DRAM)

1994-07-19

1995-10-10

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

365191, 365193, 36518905, 36523003, 3652385, G11C 700

Patent

active

054576598

ABSTRACT:
A DRAM which adapted to provide extended data output upon the input of appropriate logic signals is provided. The DRAM includes a CAS before RAS (CBR) detection circuit that controls the data output during a CBR refresh cycle. The operation of the CBR detection circuit is dependent on the state of the output enable (OE) signal during a CBR refresh cycle (e.g., WE-high, CAS-low, RAS-high then low while CAS low). If OE is low, then the CBR detection circuit will trigger a first output mode for the data out buffer (e.g., normal fast page output mode in a non-persistent version and the programmed mode in a persistent version) along with a refresh pulse to the refresh controller. If OE is high then the CBR detection circuit will trigger an extended data output from the data out buffer.

REFERENCES:
patent: 5262998 (1993-11-01), Mnich et al.
patent: 5303180 (1994-04-01), McAdams
patent: 5327387 (1994-07-01), Sugiura et al.
patent: 5349566 (1994-09-01), Merritt et al.

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