Multiple source equalization design for gate arrays and embedded

Details Multiple source equalization design for gate arrays and embedded Multiple source equalization design for gate arrays and embedded

1994-09-02

1996-04-23

Trans, Vincent N.

Boots, shoes, and leggings

364490, G06F 1750

Patent

active

055109993

ABSTRACT:
In accordance with the teachings of this invention, matched performance of alternate sourced ASICs is achieved while still allowing for the smallest die size possible from each alternate source fabrication facility. In one aspect of this invention, the width of electrical interconnects are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In another aspect, transistor channel widths are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In yet another aspect of this invention, capacitance is added to the gates of transistors to decrease their speed, when manufactured by an inherently faster process.

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