Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Patent
1995-07-13
1996-04-23
Westin, Edward P.
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
361 91, 361111, 257357, 257361, H03K 190948, H02H 904
Patent
active
055107281
ABSTRACT:
An input buffer for a CMOS integrated circuit comprises parallel pairs of complementary PMOS pull-up and NMOS pull-down transistors. Floating NMOS gates are capacitively coupled to V.sub.SS by a first-level metalization pattern. The metal-to-gate overlap capacitance and the gate-to-drain overlap capacitance define a voltage divider that leaves the gate at a small positive voltage during an electrostatic discharge event. This ensures that all NMOS transistors of a buffer enter a conducting bipolar mode before any of them enters second breakdown. This arrangement maximizes input-buffer protection from electrostatic discharge events. The novel NMOS arrangement is readily compatible with gate array designs.
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Anderson Clifton L.
Driscoll Benjamin D.
VLSI Technology Inc.
Westin Edward P.
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