Method of forming vias for multilevel metallization

Details Method of forming vias for multilevel metallization Method of forming vias for multilevel metallization

1995-05-26

1996-04-23

Hearn, Brian

Fishing, trapping, and vermin destroying

437228, 437962, 148DIG105, 148DIG106, H01L 2144, H01L 21467

Patent

active

055102948

ABSTRACT:
A method is provided for forming a via for multilevel metallization of an integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed over the integrated circuit. A first dielectric layer is then, formed over the first conductive layer. A second dielectric layer over the first dielectric layer and a second conductive layer is formed over the second dielectric layer. A photoresist layer is formed and patterned over the second conductive layer to expose a portion of the second conductive layer. The second conductive layer is etched to form an opening exposing a portion of the second dielectric layer. The second dielectric layer is then etched in the opening to form partially sloped sidewalls sloping outward at an upper surface of the dielectric layer. The photoresist layer is removed. The remaining second dielectric layer and the first electric layer is then anisotropically etched in the opening exposing the portion of the first conductive layer in the opening. The second conductive layer is then removed. A third conductive layer is deposited over the second dielectric layer and in the opening.

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patent: 4745089 (1988-05-01), Osban
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Translation of JP 62-132347 (Nase).
van den Hoek, et al., J. Vac. Sci. Technol., A7 (3) May/Jun. 1983 pp. 670-675.
S. Wolf, Silicon Processing for the VLSI Era II, Lattice Press, Sunset Beach, CA, 1990.

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