TTL to CMOS level translator with voltage and threshold compensa

Details TTL to CMOS level translator with voltage and threshold compensa TTL to CMOS level translator with voltage and threshold compensa

1996-08-27

1998-03-24

Westin, Edward P.

Electronic digital logic circuitry

Interface

Logic level shifting

326 81, H03K 19094

Patent

active

057317135

ABSTRACT:
A CMOS input buffer is described for such CMOS circuits as dynamic random access memories, microprocessors, and the like, for receiving TTL logic high and low level signals. The input buffer includes an input stage formed from a p-channel and n-channel MOS transistors configured to have substantially equal transconductances, connected to form a series current path between a bias voltage and a lower voltage (e.g., ground), setting the trip point of the input stage approximately midway between the typically specified TTL logic high and low levels. The differential between the bias and lower voltages from which the input buffer operates assures that at least one of the MOS transistors is off for a TTL logic high or low level input, obviating power consumption while the input signal is at such level. The input buffer is also made insensitive to symmetrical power supply noise, consumes less power, and is made insensitive to threshold voltage variations.

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