Method for fabricating stacked capacitors on dynamic random acce

Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device

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430320, 430323, 438396, 438948, B03C 500, H01L 2170

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active

057311307

ABSTRACT:
A method for manufacturing an array of stacked capacitors with increased capacitance for DRAM devices was achieved. The invention utilizes two photoresist masking steps and a series of self-aligning etch back steps to form a very high density array of bottom capacitor (node) electrodes. The method involves depositing and planarizing an insulating layer over the DRAM cell areas in which node contact openings (first photoresist mask) are etched to the node contact areas of the FETs. A polysilicon layer is deposited, filling the node contact openings, and patterned (second photoresist mask) to define the outer perimeters of bottom electrodes and the polysilicon layer is recessed by partially plasma etching. The second patterned photoresist mask is then laterally recessed by ashing in O.sub.2 to expose the polysilicon. A second anisotropic etch is used to form a bottom electrode having a vertical center portion and a wider base area. A conformal insulating layer is deposited and etched back to form sidewall spacers followed by a polysilicon deposition and etch back to form vertical portions on the electrode. The capacitors are then completed by removing (etching) the spacer and portions of the planar underlying layer and forming an interelectrode dielectric on the bottom electrodes and patterning another polysilicon layer to form the top electrodes.

REFERENCES:
patent: 5332685 (1994-07-01), Park et al.
patent: 5364813 (1994-11-01), Koh
patent: 5386382 (1995-01-01), Ahn
patent: 5399518 (1995-03-01), Sim et al.
patent: 5459095 (1995-10-01), Huang et al.
patent: 5620918 (1997-04-01), Kondoh

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