Processor that decodes a multi-cycle instruction into single-cyc

Details Processor that decodes a multi-cycle instruction into single-cyc Processor that decodes a multi-cycle instruction into single-cyc

1997-01-28

1999-07-13

Ellis, Richard L.

395595, 39580023, G06F 922

Patent

active

059238623

ABSTRACT:
An instruction decoder in a processor decodes an instruction by creating a decode buffer entry that includes global fields, operand fields, and a set of micro-instructions. Each micro-instruction represent an operation that an associated execution unit can execute in a single clock cycle. A scheduler issues the micro-instructions from one or more entries to the execution units for possible parallel and out-of-order execution. Each execution unit completes an operation, typically, in one clock cycle and does not monitor instructions that may block a pipeline. The execution units do not need separate decoding for multiple stages. One global field indicates which micro-instructions are execute first. Further, micro-instructions have fields that indicate an execution sequence. The scheduler issues operations in the order indicated by the global fields and the micro-instructions. When the last operation for an instruction is completed, the instruction is retired and removed from the decode buffer.

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