Electrical computers and digital processing systems: processing – Instruction alignment
Patent
1998-11-23
2000-12-12
Matar, Ahmad F.
Electrical computers and digital processing systems: processing
Instruction alignment
712206, 712214, 712215, G06F 930
Patent
active
061611727
ABSTRACT:
A method of instruction dispatch is provided in which a directly-decoded instruction and a microcode instruction are concurrently dispatched ("packed"). The instruction which is second in program order is retained until the succeeding clock cycle. During the succeeding clock cycle, a microcode unit determines if the microcode instruction and the directly-decoded instruction, when taken together, occupy less than or equal to the total number of issue positions available in the microprocessor. If the microcode unit determines that less than or equal to the total number of issue positions are occupied, then the packing is successful. If the microcode unit determines that greater than the total number of issue positions are occupied, then the packing is unsuccessful and the retained instruction is redispatched. Additionally, instruction dispatch selection is performed in two phases. First, a number of instructions are selected as potentially dispatchable instructions. From the potentially dispatchable instructions, a set of actually dispatched instructions may be selected based upon the success or failure of instruction packing during the previous clock cycle and whether or not packing was performed. If instruction packing was not performed during the previous clock cycle or was performed unsuccessfully, then the instructions which are foremost in program order within the potentially dispatchable instructions are selected. However, if instruction packing was successfully performed in the previous clock cycle, then the retained instruction is not selected for dispatch.
REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4839797 (1989-06-01), Katori et al.
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 5115500 (1992-05-01), Larsen
patent: 5167026 (1992-11-01), Murray et al.
patent: 5202967 (1993-04-01), Matsuzaki et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5233696 (1993-08-01), Suzuki
patent: 5235686 (1993-08-01), Bosshart
patent: 5337415 (1994-08-01), DeLano et al.
patent: 5371864 (1994-12-01), Chuang
patent: 5394558 (1995-02-01), Arakawa et al.
patent: 5394559 (1995-02-01), Arakawa
patent: 5430851 (1995-07-01), Hirata et al.
patent: 5459844 (1995-10-01), Eickemeyer et al.
patent: 5488710 (1996-01-01), Sato et al.
patent: 5488729 (1996-01-01), Vegesna et al.
patent: 5500942 (1996-03-01), Eickemeyer et al.
patent: 5504923 (1996-04-01), Ando
patent: 5509130 (1996-04-01), Trauben et al.
patent: 5559975 (1996-09-01), Christie et al.
patent: 5560028 (1996-09-01), Sachs et al.
patent: 5566298 (1996-10-01), Boggs et al.
patent: 5600806 (1997-02-01), Brown et al.
patent: 5619666 (1997-04-01), Coon et al.
patent: 5625787 (1997-04-01), Mahin et al.
patent: 5630083 (1997-05-01), Carbine et al.
patent: 5655097 (1997-08-01), Witt et al.
patent: 5664134 (1997-09-01), Gallup et al.
patent: 5689672 (1997-11-01), Witt et al.
patent: 5696955 (1997-12-01), Goddard et al.
patent: 5748978 (1998-05-01), Narayan et al.
patent: 5758114 (1998-05-01), Johnson et al.
patent: 5781789 (1998-07-01), Narayan
patent: 5819057 (1998-10-01), Witt et al.
patent: 5822559 (1998-10-01), Narayan et al.
patent: 5826071 (1998-10-01), Narayan
patent: 5832249 (1998-11-01), Tran et al.
Intel, "Chapter 2: Microprocessor Architecture Overview," pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Ton R. Halfhill, "AMD K6 Takes on Intel P6," BYTE, Jan. 1996, 4 pages.
Mahalingaiah Rupaka
Miller Paul K.
Narayan Rammohan
Advanced Micro Devices , Inc.
Matar Ahmad F.
Merkel Lawrence J.
Najjar Saleh
LandOfFree
Method for concurrently dispatching microcode and directly-decod does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for concurrently dispatching microcode and directly-decod, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for concurrently dispatching microcode and directly-decod will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-226721