Integrated circuit memory with multiplexed redundant column data

Details Integrated circuit memory with multiplexed redundant column data Integrated circuit memory with multiplexed redundant column data

1996-05-14

1997-09-30

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

36518902, 371 103, G11C 700

Patent

active

056732279

ABSTRACT:
An integrated circuit memory (10) has a redundant column (20) located approximately in the middle a memory array (80, 81). Input/output (I/O) blocks (49, 70) are located on a periphery of the memory (10). A redundant multiplexer (24) is coupled to the redundant column (20) and to a top redundant global data line (36) and a bottom redundant global data line (34). Data is routed between the redundant columns (20) and the I/O blocks (49, 70) via the top and bottom redundant global data lines (36, 34) to effectively shorten the redundant global data line, thereby reducing the amount of redundant data line load capacitance. A fuse circuit (50) is used to program which of the top or bottom global data lines (36, 34) replaces a defective data path. This arrangement permits increased redundant array efficiency while achieving the required performance goals.

REFERENCES:
patent: 4566081 (1986-01-01), Ochii
patent: 4601019 (1986-07-01), Shah
patent: 4660179 (1987-04-01), Aoyama
patent: 5268866 (1993-12-01), Feng
patent: 5404331 (1995-04-01), McClure

Affiliated with

Also associated with

Rating

Integrated circuit memory with multiplexed redundant column data does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit memory with multiplexed redundant column data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit memory with multiplexed redundant column data will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2261922