MOS static memory array

Static information storage and retrieval – Systems using particular element – Flip-flop

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365191, G11C 1100

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active

058944346

ABSTRACT:
A semiconductor static random access memory (RAM) array (10) is disclosed. The static RAM array (10) includes a plurality of memory cells (12), where each memory cell (12) is coupled to a write enable switch (34). The write enable switch (34) responsive to a write enable signal (36) is coupled between each memory cell (12) and a voltage source (27) or a voltage ground (29). The write enable switch (34) can disconnect each memory cell (12) from either the voltage source (27) or the voltage ground (29) responsive to the write enable signal.

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"Dynamic MOS RAM'S", R. Proebsting, ICC'77 Chicago, IEEE Catalog No. 77CHI209-6 CSCB, Conference Record vol. 3, pp. 43,4-147-43,4-150.

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