Programmable logic integrated circuit with on-chip DLL or PLL fo

Details Programmable logic integrated circuit with on-chip DLL or PLL fo Programmable logic integrated circuit with on-chip DLL or PLL fo

Filed on

1998-10-02

Date issued

2000-10-10

Examiner

Tokar, Michael

Patent Class

Electronic digital logic circuitry

SubClass

Multifunctional or programmable

SubSubClass

Array

Other Related Categories

326 39, 326 40, 326 41, 326 38, 329156, 329159, 329150, G06F 738

Type

Patent

Status

active

Patent number

061305529

Description

ABSTRACT:
A programmable logic device or field programmable gate array includes an on-chip clock synchronization circuit to synchronize a reference or system clock signal. The clock synchronization circuit is a delay-locked loop (DLL) circuit in one implementation and a phase-locked loop (PLL) circuit in another implementation. The DLL or PLL circuits may be analog or digital. The clock synchronization circuit generates a synchronized clock signal that is distributed throughout the programmable integrated circuit. The synchronized clock signal is programmably connected to the programmable logic elements or logic array blocks (LABs) of the integrated circuit. The clock synchronization circuit reduces or minimizes clock skew when distributing a clock signal within the integrated circuit. The clock synchronization circuit improves the overall performance of the programmable logic integrated circuit.

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