Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257335, 257341, 257342, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

056728948

ABSTRACT:
The resistance to electromigration in a double-layer Al wiring structure of lateral DMOS or the like is improved by further reducing ON resistance and mitigating current concentration. The first-layer source wiring and the first-layer drain wiring which are electrically connected to a plurality of source cells and drain cells respectively are formed into a pectinate pattern respectively. The second-layer source wiring and the second-layer drain wiring are also formed into a pectinate pattern respectively and disposed in inclination at 45 degrees to the patterns of the first-layer source wiring and first-layer drain wiring. At the intersections of the first-layer source wiring and the second-layer source wiring, at the intersections of the first-layer drain wiring and the second-layer drain wiring, at the outer circumferential portions of the pectinate patterns of first-layer source and drain wirings and at the source and drain pads, contact holes are provided on a layer insulation film to make a contact between the first-layer source and drain wirings and the second-layer source and drain wirings, respectively.

REFERENCES:
patent: 4636825 (1987-01-01), Baynes
patent: 4890142 (1989-12-01), Tonnel et al.
patent: 4949139 (1990-08-01), Korsh et al.
patent: 5412239 (1995-05-01), Williams

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