Integrated circuit memories and power distribution methods inclu

Details Integrated circuit memories and power distribution methods inclu Integrated circuit memories and power distribution methods inclu

1998-04-16

2000-10-10

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

257208, 257210, 257390, H01L 2710, H01L 2976

Patent

active

061304476

ABSTRACT:
At least two spaced apart control lines are located between adjacent spaced apart power lines on a memory cell array of an integrated circuit memory device. The spaced apart power lines preferably are wider than the spaced apart control lines, and the space between adjacent control lines preferably is equal to the space between a power line and an adjacent control line. Accordingly, the width of the power lines can be increased without requiring an increase in the size of the integrated circuit memory.

REFERENCES:
patent: 5698872 (1997-12-01), Takase et al.
patent: 5763908 (1998-06-01), Han et al.
Yamada et al., "A 64-Mb DRAM With Meshed Power Line", IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, pp. 1506-1509.

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