Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-03-30
2000-10-10
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438624, 438625, 438636, 438648, 438783, H01L 214763, H01L 2131
Patent
active
06130154&
ABSTRACT:
A semiconductor device with satisfactory bonding avility of a plasma SiOF oxide layer on a wiring and satisfactory burying ability for buring wiring space portions. The semiconductor device is deposited by forming a metal layer to be a base of wiring on a semiconductor substrate, forming an anti-reflection layer of a refractory metal or compound thereof, on the metal layer, and forming an insulation layer on the anti-reflection layer. There after, the insulation layer is patterned and a wiring is patterned by etching the anti-reflection layer and the metal layer to be the base of the wiring with taking the patterned insulation layer as a mask with leasing the anti-reflection layer and the insulation layer on the wiring. Subsequently, the patterned wiring is buried with an SiOF layer as an Si oxide layer containing fluorine, together with the anti-reflection layer and the insulation layer on the upper surface.
REFERENCES:
patent: 5827778 (1998-10-01), Yamada
patent: 5960310 (1999-09-01), Jeong
patent: 5960317 (1999-09-01), Jeong
Woo Sik Yoo, et al., "Intermetal Dielectric Gap Fill by Plasma Enhanced Chemical Vapor Deposited Fluorine-Doped Silicon Dioxide Films", Jpn. J. Appl. Phys., vol. 35, Part 2, No. 3A, pp. 273-275, Mar. 1996.
Kishimoto Koji
Yamada Yoshiaki
Yokoyama Takashi
Ghyka Alexander G.
NEC Corporation
Niebling John F.
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