Low-skew signal routing in a programmable array

Details Low-skew signal routing in a programmable array Low-skew signal routing in a programmable array

1995-09-28

1996-06-18

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 93, 326 39, H03K 1900, H01L 2700

Patent

active

055281702

ABSTRACT:
Providing low-skew clock signals to a Field Programmable Gate Array (FPGA) chip normally requires devoting a certain number of bondpads to that purpose. However, that limits the number of clocks that may be applied, and may also limit which bondpads can be used for that purpose. In the present invention, any input/output bondpad may be used to supply a low-skew clock, or other global type signal, to one or more of the Programmable Function Units (PFUs). This is accomplished by using a criss-crossed grid of parallel conductor groups. Any of the conductors may be supplied by a clock from a bondpad or alternatively driven directly from a PFU, thereby allowing the distribution of internally-generated clocks. To facilitate programmable interconnects between the horizontal and vertical conductors, the outer conductor in a group crosses over the others at defined intervals, to thereby become the inner conductor. In this manner, each cell may drive a subset of the conductors in a group, thereby reducing the number of drivers needed. This allows all the buffer and conductor topologies to be identical for each cell, which significantly aids in the computer-aided design of the FPGA, as well as simplifying its programming.

REFERENCES:
patent: 3987287 (1976-10-01), Cos et al.
patent: 4433331 (1984-02-01), Kollaritsch
patent: 4642487 (1987-02-01), Carter
patent: 4855619 (1989-08-01), Hsieh et al.
patent: 4870302 (1989-09-01), Freeman
patent: 5122685 (1992-06-01), Chan et al.
patent: 5144166 (1992-09-01), Camarota et al.
patent: 5153463 (1992-10-01), Keiichi
patent: 5172014 (1992-12-01), El-Ayat et al.
patent: 5212652 (1993-05-01), Agrawal et al.
patent: 5254886 (1993-10-01), El-Ayat et al.
patent: 5384497 (1995-01-01), Britton et al.
XILINX "XC4000 Logic Cell Array Family", Product Description, Dec. 1991, pp. 1-19.
electronic Design Magazine, Oct. 1, 1992, "FPGA Advances Cut Delays, Add Flexibility; Improved FPGA Architectures and Processes Increase Gate Counts, Speed, And Open New Applications." Dave Bursky.
Dwight D. Hill, et al, A New Architecture for High-Performance FPGAs, paper handed out at the Second International workshop on "Field Programmable Logic and Applications," Vienna, Austria, Aug. 31, 1992. Pp. 1-6 and FIG. 3.
1990 IEEE International Conference On computer Design: VLSI in Computers & Processors, Sep. 17-19, 1990, IEEE New York US, pp. 391-395; D. Hill et al.: "Preliminary Description of Tabula Rasa, an Electrically Reconfigurable Hardware Entine".
Electronic Engineering, vol. 64, No. 786, Jun. 1992, London GB pp. 9-10 XP000301765, "AT&T's Orthogonal ORCA Targets the FPGA Future".
Proceedings of the IEEE 1990 Custom Integrated Circuits conference, May 13-16, 1990, IEEE New York US, pp. 31.2.1-31.2.7; H.-C. Hsieh et al. "Third-Generation Architecture Boosts Speed and Density of Field-Programmable Gate Arrays".

Affiliated with

Also associated with

Rating

Low-skew signal routing in a programmable array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low-skew signal routing in a programmable array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low-skew signal routing in a programmable array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-225463