Static information storage and retrieval – Read/write circuit – Testing
Patent
1997-07-24
1999-04-20
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Testing
36523005, 371 212, G11C 2900
Patent
active
058963308
ABSTRACT:
Disclosed is an architecture of a RAM (random access memory) with BIST (built-in self test) or functional test function. The RAM has a memory cell for storing differential or single-ended binary data and bit line signals are fully differential or single-ended. Shadow write is applied to read only and read-write bit lines. With the test function, port-to-port bit line shorts and port-to-port word line shorts are sensitized.
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Silburt et al., "A 180-Mhz 0.8-.mu.m BiCMOS Modular Memory Family of DRAM and Multiport SRAM", IEEE JSSC, vol. 28, No. 3, Mar. 1993, pp. 222-232.
Nadeau-Dostie et al., "Serial Interfacing for Embedded-Memory Testing", IEEE Design & Test of Computers, Apr. 1990, pp. 52-63.
Silburt, A.L., et al, "A 180-Mhz 0.8-.mu.m BiCMOS Modular Memory Family of DRAM and Multiport SRAM", IEEE Journal of Solid-State Circuits, vol. 28, No. 3, Mar. 1993, pp. 222-232.
Nadeau-Dostie, B., et al, "Serial Interfacing for Embedded-Memory Testing", IEEE Design & Test of Computers, Apr. 1990, pp. 52-63.
de Wilton Angela C.
Nelms David C.
Northern Telecom Limited
Tran Andrew Q.
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