Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1997-10-27
1999-04-20
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
365210, G11C 1300
Patent
active
058963278
ABSTRACT:
A redundancy architecture suitable for high density integrated circuit memory, such as mask ROM is based on a two transistor redundancy cell that has a very small layout. Both row and column failure modes can be repaired. The memory used to characterize the failed row or column is implemented using an extra column or row respectively which is manufactured in a compact layout adjacent the array. Both an extra column and an extra row are laid out adjacent the array, using novel two transistor floating gate cells. Mode select logic is included by which replacement of a row or of a column is selected for the device. In the replacement row mode, a memory cell in the extra column is used to indicate the row to be replaced, and to enable the reading of the data from the replacement word line in place of the failed row. In the replacement column mode, a memory cell in the extra row is used to indicate the column to be replaced, and to enable the sensing of data from the replacement column in place of the failed column in the array.
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Fears Terrell W.
Haynes Mark A.
Macronix International Co. Ltd.
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