Thin oxide mask level defined resistor

Details Thin oxide mask level defined resistor Thin oxide mask level defined resistor

1997-09-23

1999-04-20

Martin-Wallace, Valencia

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257528, 257536, H01L 2362

Patent

active

058959602

ABSTRACT:
An integrated circuit includes a resistor formed in a doped tub located in a semiconductor substrate. A first highly doped resistor contact region extends outward from the associated contact windows towards a second highly doped resistor contact region. The extent of the underlying tub region that lies between the highly doped tub contact regions largely determines the resistance value. The size and geometry of the highly doped resistor contact regions, and hence the resistance of the resistor, is typically determined by the same mask that defines the thin oxide regions of field effect transistors formed on the IC. In a typical application, the resistor is connected between an output buffer and a bondpad. A multiplicity of output buffers on an IC chip may each connect to corresponding bondpads using a multiplicity of the inventive resistors, which may have the same, or alternatively differing, resistance values. The resistors typically are designed to have identical external dimensions, and so layout of the resistors is facilitated for various types of IC types, including for example application specific integrated circuits (ASICs).

REFERENCES:
patent: 4128845 (1978-12-01), Sakai
patent: 4167804 (1979-09-01), Greenstein
patent: 4876584 (1989-10-01), Taylor
patent: 4990802 (1991-02-01), Smooha
patent: 5300805 (1994-04-01), Demicheli et al.
patent: 5502328 (1996-03-01), Chen et al.

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