Address path architecture

Details Address path architecture Address path architecture

1996-10-23

1999-04-13

Swann, Tod R.

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

345506, 39580032, 39580043, 711 2, 711 4, 711 5, 711104, 711105, 711169, 711200, 711201, 711202, 711212, 711220, G06F 1200

Patent

active

058939326

ABSTRACT:
A microprocessor system integrated on a chip having one or more address generation devices, at least one memory location, and at least one peripheral unit. The address path is divided into two portions having a first logic unit conditioning the address from the one or more address generation devices on the first portion of the address path for gating onto the second portion of the address path. The first logic unit converts a single 16 bit address location into two 8 bit address locations. The first logic unit maintains a first address on the second address path when the CPU is in a next address pipeline mode. A second logic unit selects a memory architecture so that the system can address DRAM units having a various number of rows and/or columns.

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patent: 5175835 (1992-12-01), Beighe et al.
patent: 5603041 (1997-02-01), Carpenter et al.
patent: 5640527 (1997-06-01), Pecone
patent: 5825372 (1994-06-01), Artieri

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