Random access memory cell resistant to inadvertant change of sta

Details Random access memory cell resistant to inadvertant change of sta Random access memory cell resistant to inadvertant change of sta

1986-02-03

1988-02-16

Moffitt, James W.

Static information storage and retrieval

Systems using particular element

Flip-flop

365190, G11C 1140

Patent

active

047259817

ABSTRACT:
A static MOS RAM cell is provided that is resistant to inadvertent change of state due to charged particles striking the cell without decreasing write time. First and second cross-coupled transistors are coupled between first and second nodes, respectively, and a first voltage. First and second loads are coupled between the first and second nodes, respectively, and a second voltage. A first coupling transistor is coupled between the first node and a first input terminal, and has a gate coupled for receiving a write signal. A second coupling transistor is coupled between the second node and a second input terminal, and has a gate coupled for receiving the write signal. First and second variable loads are coupled between the first node and a gate of the second latching transistor, and the second node and a gate of the first latching transistor, respectively, for providing a resistance in the standby mode and relatively no resistance in the write mode.

REFERENCES:
patent: 4130892 (1978-12-01), Gunckel, II et al.

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