EEPROM circuit

Details EEPROM circuit EEPROM circuit

1991-09-27

1994-08-09

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Erase

36518904, G11C 700

Patent

active

053372808

ABSTRACT:
An EEPROM circuit has two memory transistors in a memory cell of an array. Stored data is read out to a reading circuit via a first and second complementary bit lines. A writing circuit provides voltage to the cell so that the first memory transistor writes data and the second memory transistor erases data. An erasing circuit does the converse, i.e. provides voltage to the cell so that the first memory transistor erases data and the second memory transistor writes data.

REFERENCES:
patent: 4279024 (1981-07-01), Schrenk
patent: 4803662 (1989-02-01), Tanaka
patent: 4903236 (1990-02-01), Nakayama
patent: 4931997 (1990-06-01), Mitsuishi
patent: 4958326 (1990-09-01), Sakurai
patent: 5097446 (1992-03-01), Shoji
patent: 5111427 (1992-05-01), Kobayashi

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