Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1994-09-16
1997-09-16
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326101, H03K 1901
Patent
active
056684843
ABSTRACT:
A clock signal distribution circuit of a tree structure having a plurality of buffers arranged in a plurality of hierarchical stages includes short-circuit wirings for short-circuiting output terminals of the buffers at each stage of the plurality of hierarchical stages. Each of the plurality of buffers is formed by a single inverter or a multi-stage inverter wherein an input stage inverter and an output stage inverter are connected in series. The output stage inverter has a size larger than that of the input stage inverter. The clock signal distribution circuit thus constructed can reduce clock skew and distribute a high frequency clock signal having sharp rise and fall characteristics to a plurality of registers.
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Driscoll Benjamin D.
NEC Corporation
Westin Edward P.
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