Method for preparing a chip scale package and product produced b

Details Method for preparing a chip scale package and product produced b Method for preparing a chip scale package and product produced b

1998-01-08

2000-09-05

Niebling, John F.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

438108, 438612, 438613, 2989001, 2281791, H01L 2144, H01L 2148, H01L 2150

Patent

active

061141879

ABSTRACT:
Solder jetting technology is employed to prepare a chip scale package which is "bumped" in preparation for making electrical interconnections with pads on a connection surface of the chip. The chip scale packages can be produced in wafer form before severing the wafer to produce individually packaged chips. In one embodiment a column is built on each pad of the chip connection surface and then the pads and columns are covered with a layer of dielectric jetted on to the connection surface to provide the package. The upper surface portion of the dielectric layer is removed to expose the ends of the columns. The ends of the columns are then bumped using solder jet technology to ready the package for subsequent electrical interconnections. An alternate embodiment employs taller columns which extend above the layer of dielectric. A solder reflow operation is applied to convert the exposed upper ends of the columns into generally spherical balls. The technique also allows vertical solder columns to be extended laterally along the surface of a first dielectric layer and a second dielectric layer applied wherein a second vertical portion of column is bumped in order to make a connection.

REFERENCES:
patent: 3683212 (1972-08-01), Zoltan
patent: 3857049 (1974-12-01), Zoltan
patent: 5433809 (1995-07-01), Pies et al.
patent: 5436648 (1995-07-01), Stortz et al.
patent: 5461403 (1995-10-01), Wallace et al.

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