Shallow-implant elevated source/drain doping from a sidewall dop

Details Shallow-implant elevated source/drain doping from a sidewall dop Shallow-implant elevated source/drain doping from a sidewall dop

1998-08-26

2000-12-12

Abraham, Fetsum

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257336, 257338, 257344, H01L 31119

Patent

active

06160299&

ABSTRACT:
A structure having shallow-implanted elevated source/drain regions is formed with doped sidewall spacers. Diffusion of dopants from the sidewall spacers forms a doped region extending from underneath the gate electrode, along the edge of the epitaxial layer, to the doped (and uppermost) regions of the elevated source/drain. Low junction capacitance, is achieved because the shallow implant of the elevated source/drain regions places the junction inside the source/drain region itself. Low source/drain resistance is achieved because the diffused doped region provides a doped path between the shallow implanted region of the elevated source/drain and the channel region. Low source/drain junction depth is achieved because a second spacer can prevent dopant from being implanted through any faceted areas of the epitaxial layer. The doped extensions of the source/drain regions also have exceptionally low junction depth. The overall process is simpler because it is independent of both facet angle and height of the epitaxial layer.

REFERENCES:
patent: 5079180 (1992-01-01), Rodder et al.
patent: 5496750 (1996-03-01), Moslehi
patent: 5640037 (1997-06-01), Blanchard
patent: 5663079 (1997-09-01), Blanchard
IEEE Electron Device Letters, vol. 10, No. 10, Oct. 1989, "Reverse Short-Channel Effects on Threshold Voltage in Submicrometer Salicide Devices," pp. 446-448 (Chih-Yuan Lu, Senior Member, IEEE and J.M. Sung).
IEEE Electron Device Letters, vol. 18, No. 6, Jun. 1997, "0.18-.mu.m Fully-Depleted Silicon-On-Insulator MOSFET's," pp. 251-253 (Min Cao, Member IEEE, Ted Kamins, Fellow IEEE, Paul Vande Voorde, Member IEEE, Carlos Diaz, Member IEEE, and Wayne Greene, Member IEEE).
1992 IEEE, IEDM 92-885, "Reverse Elevated Source/Drain (RESD) MOSFET for Deep Submicron CMOS," pp. 23.2.1-35.2.4 (J.R. Pfiester, M. Woo, J.T. Fitch and J. Schmidt).
1993 IEEE, IEDM 93-119, "Sub-50 NM Gate Length N-MOSFETs With 10 NM Phosporus Source and Drain Junctions," pp. 6.2.1-6.2.4 (Mizuki Ono, Masanobu Saito, Takashi Yoshitomi, Claudio Fiegna, Tatsuya Ohguro and Hiroshi Iwai).
1992 IEEE, IEDM 92-853, "Facet Engineered Elevated Source/Drain by Selective Si Epitaxy for 0.35 Micron MOSFETs," pp. 33.7.1-33.7.4 (Carlos Mazure, Jon Fitch and Craig Gunderson).
1992 IEEE, IEDM 92-855, "Reverse Elevated Source/Drain (RESD) MOSFET for Deep Submicron CMOS," pp. 35.2.1-35.2.4 (J.R. Pfiester, M. Woo, J.T. Fitch and J. Schmidt).
IEEE Electron Device Letters, vol. 12, No.3, Mar.1991, "Raised Source/Drain MOSFET With Dual Sidewall Spacers," pp. 89-91 (Mark Rodder, Member IEEE, and D. Yeakley).

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