High speed programmable logic architecture

Details High speed programmable logic architecture High speed programmable logic architecture

1995-06-05

1997-03-25

Westin, Edward P.

Electronic digital logic circuitry

Interface

Current driving

326 48, 326 50, 326110, H03K 19082, H03K 190948

Patent

active

056148445

ABSTRACT:
Architecture for a programmable logic device is described which can operate at substantially faster clock rates than present programmable logic devices. The PLD uses BiCMOS circuit elements to make use of the speed advantages of bipolar technology while also enjoying the limited power consumption of CMOS technology.

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