Structure and method for improved storage node isolation

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257327, 257344, 257335, 257373, 257408, H01L 2976, H01L 2994

Patent

active

057639167

ABSTRACT:
A MOS gate and associated source/drain region structure providing three junction diodes between a source/drain contact area and the substrate, instead of the typical total of one, resulting in improved isolation of a source/drain contact area and a storage node which may be formed thereat. For fabricate the structure, a source/drain region is formed in a substrate having a space charge in the bulk or major part thereof, the source/drain region including: a first region having a space charge with a polarity opposite that of a space charge in the major part of the substrate; a second region separated from the major part of the substrate by the first region and having a space charge with a polarity opposite that of the space charge of the first region; and a third region separated from the first region and the major part of the substrate by the second region and having a space charge with a polarity opposite that of the space charge of the second region. The first and second regions extend laterally under an associated gate. The third region extends laterally to the boundary of the region under the gate, and does not extend under the gate. The third region includes a portion of the surface of the substrate corresponding to a source/drain contact area. The source/drain region may be prepared by successive angled implants of alternating polarity. A storage node may then be formed above the third region.

REFERENCES:
patent: 5426326 (1995-06-01), Ohyu et al.
patent: 5532508 (1996-07-01), Kaneko et al.

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