Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1991-05-13
1994-04-19
Hille, Rolf
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257369, 257371, 257373, H01L 2976, H01L 2994, H01L 31062, H01L 31119
Patent
active
053048334
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a complementary MOS semiconductor device having a structure suitable for improvement of resistance to latchup.
BACKGROUND ART
In the art of complementary MOS semiconductor device (hereinafter referred to as CMOS) comprising p-channel and n-channel transistors, it has been increasingly demanded to establish a fine topographic technology with the need for high density and high integration while making the use of an advantage of small power consumption.
With regard to the structure of CMOS, a bipolar parasitic transistor circuit is arranged in the internal part in the same arrangement as thyrister. As a result, a problem exists in that when triggered by surge or the like from outside, an excessively large current may flow from power terminal to ground terminal causing thereby a phenomenon of latchup in which current still continues to flow even after disappearance of surge or the like, eventually resulting in breakdown of the device due to such large current. Under such circumstances, it may be said that a novel structure of CMOS is essential from the viewpoint of improvement of resistance to latchup, though requirements of the resistance will be more strict under the recent need for finer topography. Among several proposals ant attempts, retrograde well structure is known. FIG. 11 is a structural sectional view and circuit diagram schematically illustrating a structure of a CMOS inverter arranged in the simplest manner and a parasitic thyrister equivalent circuit.
In FIG. 11, reference numeral (1) indicates a p-type silicon semiconductor substrate of 1.times.10.sup.15 cm.sup.-3 in concentration and 10 .OMEGA..multidot.cm in resistivity; numeral (2) indicates a field oxide film which is formed on one main surface of the mentioned p-type semiconductor substrate (1) and serving as a device separating region; numeral (3) indicates a n-well region which is formed by carrying out first implantation of phosphorus ion into an island-shaped region formed being separated by the mentioned field oxide film (2) on condition of 700 kev in acceleration voltage and 1.times.10.sup.13 cm in dose, and second implantation of phosphorus ion on condition of 200 kev in acceleration voltage and 1.times.10.sup.12 cm.sup.-2 in dose; numeral (4) indicates a bottom part of higher impurity concentration (1.times.10.sup.16 to 1.times.10.sup.17 cm.sup.-3) in the mentioned n-well region (3); numeral (5) indicates a p-well region which is formed by carrying out first implantation of boron ion into a region adjacent the mentioned island-shaped n-well region (3) formed being separated by the mentioned field oxide film (2) on condition of 400 kev in acceleration voltage and 1.times.10.sup.13 cm.sup.-2 in dose, and second implantation of boron ion on condition of 100 kev in acceleration voltage and 1.times.10.sup.12 cm.sup.-2 in dose; numeral (6) indicates a bottom part of higher impurity concentration (1.times.10.sup.16 to 1.times.10.sup.17 cm.sup.-3) in the mentioned p-well region (5); numeral (7) indicates a n.sup.+ -type well contact region for supplying potential to the mentioned n-well region (3); numeral (8) indicates a p.sup.+ -type well contact region for supplying potential to the mentioned p-well region (5); numeral (9a) indicates a p.sup.+ -type source region arranged in the mentioned n-well region (3) to form a p-channel transistor of the CMOS inverter; numeral (9b) indicates a p.sup.+ -type drain region arranged in the mentioned n-well region (3) to form a p-channel transistor of the CMOS inverter together with the mentioned p.sup.+ -type source region (9a); numeral (10a) indicates a n.sup.+ -type source region arranged in the mentioned p-well region (5) to form a n-channel transistor of the CMOS inverter; numeral (10b) indicates a n.sup.+ -type drain region arranged in the mentioned p-well region (5) to form a n-channel transistor of the CMOS inverter together with the mentioned n.sup.+ -type source region (10a); numeral (11a) indicates a gate electrode of the p-channel transis
REFERENCES:
patent: 5138420 (1992-08-01), Komori et al.
Katsuyoshi Mitsui
Shigeki Komori
Fahmy Wael
Hille Rolf
Mitsubishi Electric Corporation
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