Static information storage and retrieval – Read/write circuit – Testing
Patent
1994-07-29
1996-02-06
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Testing
371 213, 371 27, G11C 700
Patent
active
054901154
ABSTRACT:
A computer memory system incorporates a gang write circuit block to reduce the number of clock cycles required write a background pattern to memory cells during a memory test operation. The computer memory system includes (1) a two-dimensional array having multiple memory cells arranged in M rows and N columns and (2) the gang write circuit block for writing to N memory cells located in a row during one cycle and for writing to all of the memory cells in M cycles. The gang write circuit block may include two inverters for each column of the memory array and two test signals for the inverters. The background pattern may be all 1's, all 0's or some combination of 1's and 0's. The gang write circuit block becomes inactive during a normal read and write operation. When all the word lines of the computer memory system are selected, all the memory cells are written simultaneously.
REFERENCES:
patent: 4701919 (1987-10-01), Naitoh et al.
patent: 4788684 (1988-11-01), Kawaguchi et al.
patent: 4821238 (1989-04-01), Tatematsu
patent: 4885748 (1989-12-01), Hoffmann et al.
Landry Gregory J.
Shah Shailesh
Cypress Semiconductor Corp.
Dinh Son
Nelms David C.
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