Single stage dynamic receiver/decoder

Details Single stage dynamic receiver/decoder Single stage dynamic receiver/decoder

1995-06-07

1997-06-17

Hudspeth, David R.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326 98, H03K 190175

Patent

active

056401086

ABSTRACT:
A high performance receiver/decoder circuit combines input signal detection and decoding to a one-of-n selection signal in a single stage. Particularly when implemented in dynamic logic, speed of decoding is substantially increased while reset and precharge circuits and procedures are greatly simplified which is accomplished by placing logic trees in series with a latch circuit and a common connection to a transistor or other circuit for enabling input evaluation. The decoder is preferably implemented with a plurality of identical circuits with true and complement inputs selectively distributed thereto, as may be convenient to the circuit design.

REFERENCES:
patent: 4570084 (1986-02-01), Griffin et al.
patent: 4684829 (1987-08-01), Uratani
patent: 4953130 (1990-08-01), Houston
patent: 5015882 (1991-05-01), Houston et al.
patent: 5047983 (1991-09-01), Iwai et al.
patent: 5161120 (1992-11-01), Kajimoto et al.
patent: 5200926 (1993-04-01), Iwahashi et al.
patent: 5329176 (1994-07-01), Miller, Jr. et al.

Affiliated with

Also associated with

Rating

Single stage dynamic receiver/decoder does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Single stage dynamic receiver/decoder, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Single stage dynamic receiver/decoder will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2160498