Standby redundancy system

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

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Details

714 13, 714 6, G06F 1214

Patent

active

059789328

ABSTRACT:
A standby redundancy system comprising a control CPU unit for controlling controlled machines and a standby CPU unit capable of controlling the controlled machines instead of the control CPU unit, characterized by tracking unit for temporarily storing a command consisting of a statement and data entered from a peripheral machine, processing the data based on the statement in the command, and transferring the temporarily stored command to the associated CPU unit.

REFERENCES:
patent: 3964055 (1976-06-01), Carruet et al.
patent: 4564900 (1986-01-01), Smitt
patent: 5249187 (1993-09-01), Bruckert et al.
patent: 5751955 (1998-05-01), Sonnier et al.
patent: 5841963 (1997-05-01), Nakamikawa et al.
patent: 5857208 (1996-05-01), Ofek

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