Semiconductor memory device with planarization structure

Details Semiconductor memory device with planarization structure Semiconductor memory device with planarization structure

1995-06-01

1997-03-04

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257350, 257395, 257401, 257508, 257296, 257630, H01L 218242

Patent

active

056082487

ABSTRACT:
A first interlayer insulating layer is formed on a main surface of a substrate. A semiconductor layer is formed on the first interlayer insulating layer. A gate electrode (word line) of a switch MOS transistor is formed under the semiconductor layer. A bit line and a capacitor are formed on the semiconductor layer. The semiconductor layer has a substantially flat upper surface, and an interlayer insulating layer and a second interlayer insulating layer having substantially flat upper surfaces are formed on the semiconductor layer. A capacitor is formed on the second interlayer insulating layer, and the capacitor and the second interlayer insulating layer are covered with a third interlayer insulating layer. Thereby, a level difference between a memory cell array and a peripheral circuitry can be reduced in a semiconductor memory device.

REFERENCES:
patent: 4561170 (1985-12-01), Doering
patent: 5218217 (1993-06-01), Oda
patent: 5486712 (1996-01-01), Arima

Affiliated with

Also associated with

Rating

Semiconductor memory device with planarization structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with planarization structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with planarization structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2148061