Static information storage and retrieval – Read/write circuit – With shift register
Patent
1992-02-11
1995-08-22
Harvey, Jack B.
Static information storage and retrieval
Read/write circuit
With shift register
36523006, 365239, 365240, G11C 700, G11C 800, G11C 1900
Patent
active
054446600
ABSTRACT:
A sequential access memory employs a dynamic type row address pointer 2 as a row address pointer for selecting row selection lines of a memory cell array 1, and a static type column address pointer 3 as a column address pointer for selecting a column selection lines 5 of memory cell array 1.
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Y. Suzuki et al., "Clocked CMOS Calculator Circuitry" IEEE Journal of Solid-State Circuits, vol. sc-8, No. 6, Dec. 1973, pp. 462-469.
Kimura Masatoshi
Yamanaka Kazuya
Harvey Jack B.
Mitsubishi Denki & Kabushiki Kaisha
Whitfield Michael A.
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