All-CMOS high-impedance output buffer for a bus driven by multip

Details All-CMOS high-impedance output buffer for a bus driven by multip All-CMOS high-impedance output buffer for a bus driven by multip

1994-10-05

1995-08-22

Hudspeth, David R.

Electronic digital logic circuitry

Interface

Supply voltage level shifting

326 58, 326 27, 327 57, H03K 190175, H03K 1902

Patent

active

054443970

ABSTRACT:
An all-CMOS output buffer drives a bus that can operate at 3 volts and 5 volts. When in a high-impedance state, the output buffer draws little or no current. If the bus is driven to 5 volts by an external device, the high impedance output buffer is in danger of latch-up and distortion of the bus logic level since it only has a 3-volt power supply and does not use a charge pump or an extra 5-volt supply. A biasing circuit couples an N-well that contains p-channel transistors and a driver transistor to the bus driven to 5 volts. Thus the N-well is also driven to 5 volts, the voltage on the bus. The gate of the p-channel driver transistor in the high-impedance output buffer is also coupled to the N-well by another p-channel transistor, raising the gate potential to 5 volts. Thus the gate and body of the p-channel driver transistor is at 5 volts, eliminating reversing current and latch-up problems. A transmission gate isolates the gate of the p-channel driver transistor from the rest of the device's circuitry. The p-channel transistors of the transmission gate, bias circuitry, and driver transistor are located in the N-well, which is biased up to 5 volts only when necessary. Thus during normal operation, the N-well of the driver transistor is at 3 volts, eliminating a performance loss from the body effect. A logic gate increases the well bias and isolates the driver's gate only when necessary, when the bus is high and driven by a 5-volt device, and the output buffer is in high-impedance.

REFERENCES:
patent: 4871927 (1989-10-01), Dallavalle
patent: 4963766 (1990-10-01), Lundberg
patent: 5117129 (1992-05-01), Hoffman et al.
patent: 5144165 (1992-07-01), Dhong
patent: 5266849 (1993-11-01), Kitahara
patent: 5300835 (1994-04-01), Assar
patent: 5381061 (1995-01-01), Davis
"Crossvolt Low Voltage Logic Series Databook", National Semiconductor Corp., 1994, pp. 1-13.

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