Input/output circuit having the input buffer circuit being conne

Details Input/output circuit having the input buffer circuit being conne Input/output circuit having the input buffer circuit being conne

1994-03-09

1995-05-23

Hudspeth, David R.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

326 33, 326 34, H03K 1716

Patent

active

054184754

ABSTRACT:
An input terminal is connected commonly with a first transistor gate and drain and a second transistor source having the same polarity with the first transistor. A first transistor source is connected to a voltage source. A second transistor gate is connected to the voltage source through a variable voltage source. A second transistor drain terminal is used as a current output terminal, and an input terminal is used as a voltage output terminal. The input circuit is capable of obtaining a current gain approximating "1" while input impedance variation due to input signal variation maintain suppressed smaller.

REFERENCES:
patent: 4859877 (1989-08-01), Cooperman et al.
patent: 4970419 (1990-11-01), Hagen et al.
patent: 5023488 (1991-06-01), Gunning
patent: 5029284 (1991-07-01), Feldbaumer et al.
patent: 5084637 (1992-01-01), Gregor
patent: 5107230 (1992-04-01), King
patent: 5208492 (1993-05-01), Masumoto et al.
patent: 5227677 (1993-07-01), Furman
patent: 5341039 (1994-08-01), Fukumoto
IBM Technical Disclosure Bulletin, vol. 32, No. 4A, Sep. 1989, pp. 393-395.
"A Study of 156 Mbps CMOS Driver-Receiver", Daijiro Inami, et al., Proceedings of the 1991 IEICE Spring Conference, C-634, pp. 5-225.

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