Apparatus for controlling the transfer of interrupt signals in d

Details Apparatus for controlling the transfer of interrupt signals in d Apparatus for controlling the transfer of interrupt signals in d

1984-04-09

1987-01-20

Williams, Jr., Archie E.

Boots, shoes, and leggings

371 7, 371 11, 371 13, G06F 1100, G06F 1130, G06F 1324

Patent

active

046384324

ABSTRACT:
To ensure security of interrupt input signals to a computer system (30-3N) with minimum interruption of the running of programs in the system, two interrupt logic units (1) receive interrupt signals on leads (20-2x) from connected apparatus and store flags representing the interrupt signals in an interrupt store (2). Control logic (3) compares each input signal with presettable criteria to determine if such signal is an interrupt signal and, if so, causes the data to be transferred by way of a read register (5) to the connected computer system (30-3N). At the same time the control logic (3) of one of the units (1) designated as the active unit also causes an ouput on a lead (11) to the other unit (1) designated as the standby unit. If the standby unit determines that an immediate interrupt has occurred and does not receive a signal on the lead (11), its respective control logic (3) will cause the contents of its interrupt store (2) to be transferred to its respective read register (5) and will also cause an additional flag to be entered in the read register (5) indicating the failure of the active unit (1). Designation of the two units (1) as "active" or "standby" is periodically changed by action of the computer system (30-3N).

REFERENCES:
patent: 3895353 (1975-07-01), Dalton
patent: 3908099 (1975-09-01), Borbas et al.
patent: 4371754 (1983-02-01), De et al.
patent: 4412280 (1983-10-01), Murphy et al.
J. L. Hufferd, Reliability in Multiprocessors Through Swapping Status of a Failing CPU Alternately with Status of a Non-Failing CPU; IBM Technical Disclosure Bulletin (vol. 14, No. 7, Dec. 1971), pp. 1968-1970.

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