Semiconductor memory device having two layers of bit lines arran

Details Semiconductor memory device having two layers of bit lines arran Semiconductor memory device having two layers of bit lines arran

1996-07-24

1997-12-16

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365 63, 365 51, G11C 700, G11C 506

Patent

active

056993080

ABSTRACT:
In a semiconductor memory cell array including word lines, bit lines, and a plurality of memory cells arranged at crossings between the word lines and the bit lines, the bit lines are grouped into odd and even numbered groups. A shift redundancy circuit is arranged between each group of odd or even bit lines and sense amplifier and write circuits for the purpose of shifting a defective memory cell to a redundant memory cell.

REFERENCES:
patent: 4367540 (1983-01-01), Shimohigashi
patent: 4907203 (1990-03-01), Wada et al.
patent: 5014241 (1991-05-01), Asakura et al.
patent: 5214641 (1993-05-01), Hidaka et al.
patent: 5280441 (1994-01-01), Wada et al.
"Bit Line Configuration Suitable for Very High Speed SRAM - T-Shaped Bit Line Configuration and Application to BiCMOS 256K TTL SRAM", T. Kenkyukai et al., pp. 117-123, Jun. 21, 1991.
"A 5.8-NS 256-KB BiCMOS TTL SRAM with T-shaped Bit Line Architecture", Toru Shiomi et al., IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993.
"New Bit Line Architecture for Ultra High Speed SRAMS", Shiomi et al., IEEE 1991 Custom Integrated Circuits Conference.

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