Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Patent
1996-05-13
1997-12-16
Yoo, Do Hyun
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
365193, 36523003, 365233, G11C 1300
Patent
active
056993030
ABSTRACT:
When an external RAS and external CAS are input to a RAS buffer and a CAS buffer, an internal RAS and an internal CAS are generated. The internal RAS is input to a clock generating circuit and a CBR mode determination circuit and the internal CAS is input to the CBR mode determination circuit. The clock generating circuit outputs a pump clock to first and second WL pumps upon input of internal RAS, and the first WL pump supplies charge to a Vpp power supply. If CAS is input prior to RAS during refresh operation, CBR mode determination circuit inputs a CBR mode signal to the second WL pump which supplies charge to Vpp power supply together with the first WL pump when the pump clock and the CBR mode signal is input thereto.
REFERENCES:
patent: 5410507 (1995-04-01), Tazunoki et al.
patent: 5436586 (1995-07-01), Miyamoto
patent: 5568440 (1996-10-01), Tsukude et al.
patent: 5587956 (1996-12-01), Tanida
patent: 5604707 (1997-02-01), Kuge et al.
K. Kenmizaki, et al. "A 36uA 4Mb PSRAM with Quadruple Array Operation", VLSI Circuits Symposiom Digest, 1989, pp. 79-80.
Furutani Kiyohiro
Hamamoto Takeshi
Morooka Yoshikazu
Mitsubishi Denki & Kabushiki Kaisha
Yoo Do Hyun
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